Generally, an image sensor is a semiconductor device that transforms an optical image to an electric signal. An image sensor can be classified as a charge coupled device (CCD) or a complementary metal oxide silicon (CMOS) image sensor.
The CCD has shortcomings such as a complicated driving method and high power consumption. Also, the fabricating method of the CCD is complicated because a multi-level photolithography process is required.
Therefore, the CMOS image sensor has received attention as a next-generation image sensor to overcome the shortcomings of the CCD.
The CMOS image sensor is a device employing a switching mode that sequentially detects outputs of each unit pixel using MOS transistors. The switching mode incorporates MOS transistors at each unit pixel formed on a semiconductor substrate and a control circuit and a signal processing circuit as peripheral circuits.
The CMOS image sensor can be classified into types such as a 3T type, a 4T type, and a 5T type, according the number of transistors. For example, the 3T type CMOS image sensor includes one photodiode and three transistors, and the 4T type CMOS image sensor includes one photodiode and four transistors.
Hereinafter, the unit pixel of the 4T type CMOS image sensor will be described with reference to a plan view thereof.
As shown in FIG. 1, the unit pixel of the CMOS image sensor according to the prior art includes a photodiode 10 and four transistors as an optoelectric converter. The four transistors are a transfer transistor 20, a reset transistor 30, an access transistor 40 and a select transistor 50. In FIG. 1, FD denotes a floating diffusion region and a numeral reference 90 denotes a coupling portion connecting the FD and the access transistor 40. Vin denotes an input terminal, and Vout denotes an output terminal.
Hereinafter, the photodiode 10 and the transfer transistor 20 in the CMOS image sensor according to the prior art will be described with reference to a cross-section view through line I-I′.
As shown in FIG. 2, the transfer transistor 20 includes a gate insulating layer 21 and a gate electrode 23 formed on a substrate 11, and a first sidewall 29 and a second sidewall 31 formed at both sides of the gate electrode 23.
In addition, an n− type diffusion region (N−) 28 and a Po type diffusion region (PDP; P type photodiode implant) 35 are formed at the photodiode region (PD) of the substrate 11. The Po type diffusion region 35 is formed on the n− type diffusion region 28. Also, a heavily doped n+ type diffusion region (N+) 32 and a lightly doped n− type diffusion region (N−) 26 are formed at the floating diffusion region (FD) of the substrate 11.
FIG. 3 is a cross-sectional view for describing one of the fabricating processes for a CMOS image sensor according to the prior art.
As shown in FIG. 3, a photoresist layer 27 is applied on an entire surface of the substrate 11, and the applied photoresist layer 27 is patterned to expose the photodiode region (PD) through an exposing and developing process.
Then, the lightly doped n− type diffusion region 28 is formed at the photodiode region by implanting an n type impurity ion in to the substrate 11 with an ion implantation energy of 100 KeV to 500 KeV using the patterned photoresist layer 27 as a hard mask.
The impurity ion implantation for forming the lightly doped n− type diffusion region 28 at the photodiode region is performed with the ion implanting energy higher than that for forming the lightly doped n− type diffusion region 26 at the floating diffusion region such that the lightly doped n− type diffusion region 28 is formed more deeply into the substrate.
However, the method for fabricating the CMOS image sensor according to the prior art has problems as follows.
That is, in order to use the n− type diffusion region 28 formed at the photodiode region as the source of the transfer transistor 20, a predetermined region of the upper portion of the gate electrode 23 must be exposed during the photolithography process.
In particular, the photoresist layer 27 does not cover the entire transfer transistor 20. For example, the photoresist layer 27 is applied to expose a predetermined portion of the gate electrode 23 in a source side so that the photoresist layer 27 is self-aligned at the gate electrode 23 when the ion implantation process is performed.
The impurity ion is also implanted at the exposed portion A of the gate electrode 23 because of the ion implantation energy applied such as in a range from 100 KeV to 500 KeV when the ion implantation is performed for forming the n− type diffusion region 28. Therefore, a characteristic of the transfer transistor 20 is changed and a characteristic of the image sensor can also be degraded thereby.